pdu13f doc #97001 data delay devices, inc. 1 1/10/97 3 mt. prospect ave. clifton, nj 07013 3-bit programmable delay line (series pdu13f) features packages digitally programmable in 8 delay steps monotonic delay-versus-address variation two separate outputs: inverting & non-inverting precise and stable delays input & outputs fully ttl interfaced & buffered 10 t 2 l fan-out capability fits standard 14-pin dip socket auto- insertable functional description the pdu13f-series device is a 3-bit digitally programmable delay line. the delay, td a , from the input pin (in) to the output pins (out, out/) depends on the address code (a2-a0) according to the following formula: td a = td 0 + t inc * a where a is the address code, t inc is the incremental delay of the device, and td 0 is the inherent delay of the device. the incremental delay is specified by the dash number of the device and can range from 0.5ns through 50ns, inclusively. the enable pin (en/) is held low during normal operation. when this signal is brought high, out and out/ are forced into low and high states, respectively. the address is not latched and must remain asserted during normal operation. series specifications total programmed delay tolerance: 5% or 1ns, whichever is greater inherent delay (td 0 ): 6ns typical (out) 5.5ns typical (out/) setup time and propagation delay: address to input setup (t ais ): 6ns disable to output delay (t diso ): 6ns typ. (out) operating temperature: 0 to 70 c temperature coefficient: 100ppm/ c (excludes td 0 ) supply voltage v cc : 5vdc 5% supply current: i cch = 45ma i ccl = 20ma minimum pulse width: 20% of total delay 1997 data delay devices data delay devices, inc. 3 pdu13f-xxmc3 military gull-wing 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in n/c n/c n/c out out/ en/ gnd vcc n/c n/c n/c n/c a0 a1 a2 14 13 12 11 10 9 8 1 2 3 4 5 6 7 in n/c n/c out out/ en/ gnd vcc n/c n/c n/c a0 a1 a2 pdu13f-xx dip pdu13f-xxa2 gull-wing pdu13f-xxb2 j-lead pdu13f-xxm military dip pin descriptions in delay line input out non-inverted output out/ inverted output a2 address bit 2 a1 address bit 1 a0 address bit 0 en/ output enable vcc +5 volts gnd ground dash number specifications part number incremental delay per step ( ns) total delay change ( ns) pdu13f-.5 .5 .3 3.5 1.0 pdu13f-1 1 .4 7 1.0 pdu13f-2 2 .4 14 1.0 pdu13f-3 3 .5 21 1.1 pdu13f-5 5 .6 35 1.8 pdu13f-10 10 1.0 70 3.5 pdu13f-15 15 1.3 105 5.3 pdu13f-20 20 1.5 140 7.0 pdu13f-40 40 2.0 280 14.0 pdu13f-50 50 2.5 350 17.5 note: any dash number between .5 and 50 not shown is also available.
pdu13f doc #97001 data delay devices, inc. 2 1/10/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com application notes address update the pdu13f is a memory device. as such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. the timing restrictions are shown in figure 1. after the last signal edge to be delayed has appeared on the out pin, a minimum time, t oax , is required before the address lines can change. this time is given by the following relation: t oax = max { (a i - a i-1 ) * t inc , 0 } where a i-1 and a i are the old and new address codes, respectively. violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the out pin. the possibility of spurious signals persists until the required t oax has elapsed. a similar situation occurs when using the en/ signal to disable the output while in is active. in this case, the unit must be held in the disabled state until the device is able to ?clear? itself. this is achieved by holding the en/ signal high and the in signal low for a time given by: t dish = a i * t inc violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the out pin. the possibility of spurious signals persists until the required t dish has elapsed. input restrictions there are three types of restrictions on input pulse width and period listed in the ac characteristics table. the recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. the suggested conditions are those for which signals will propagate through the unit without significant distortion. the absolute conditions are those for which the unit will produce some type of output for a given input. when operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. however, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. in other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. please consult the technical staff at data delay devices if your application has specific high-frequency requirements. please note that the increment tolerances listed represent a design goal. although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. monotonicity is, however, guaranteed over all addresses. t diso t oax t aens t enis pw in td a pw out t dish a2-a0 en/ in out out/ figure 1: timing diagram a i-1 a i t skew t ais
pdu13f doc #97001 data delay devices, inc. 3 1/10/97 3 mt. prospect ave. clifton, nj 07013 device specifications table 1: ac characteristics parameter symbol min typ units total programmable delay td t 7 t inc inherent delay td 0 6.0 ns output skew t skew 1.5 ns disable to output low delay t diso 6.0 ns address to enable setup time t aens 2.0 ns address to input setup time t ais 6.0 ns enable to input setup time t enis 6.0 ns output to address change t oax see text disable hold time t dish see text absolute per in 20 % of td t input period suggested per in 50 % of td t recommended per in 200 % of td t absolute pw in 10 % of td t input pulse width suggested pw in 25 % of td t recommended pw in 100 % of td t table 2: absolute maximum ratings parameter symbol min max units notes dc supply voltage v cc -0.3 7.0 v input pin voltage v in -0.3 v dd +0.3 v storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 3: dc electrical characteristics (0c to 70c, 4.75v to 5.25v) parameter symbol min typ max units notes high level output voltage v oh 2.5 3.4 v v cc = min, i oh = max v ih = min, v il = max low level output voltage v ol 0.35 0.5 v v cc = min, i ol = max v ih = min, v il = max high level output current i oh -1.0 ma low level output current i ol 20.0 ma high level input voltage v ih 2.0 v low level input voltage v il 0.8 v input clamp voltage v ik -1.2 v v cc = min, i i = i ik input current at maximum input voltage i ihh 0.1 ma v cc = max, v i = 7.0v high level input current i ih 20 m a v cc = max, v i = 2.7v low level input current i il -0.6 ma v cc = max, v i = 0.5v short-circuit output current i os -60 -150 ma v cc = max output high fan-out 25 unit output low fan-out 12.5 load
pdu13f doc #97001 data delay devices, inc. 4 1/10/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com package dimensions .790 max. 1 2 3 4 5 6 7 8 .320 typ. .020 typ. .040 typ. .100 .110 .600 .350 max. .270 typ. .050 typ. .110 typ. 9 10 11 12 13 14 commercial j-lead (pdu13f-xxb2) .820 max. 1 2 3 4 5 6 7 8 14 13 12 11 10 9 .290 max. .015 typ. .070 max. .018 typ. .600 .010 6 equal spaces each .100 .010 non-accumulative .280 max. .350 max. .010 .002 lead material: nickel-iron alloy 42 tin plate commercial dip (pdu13f-xx) .790 max. .430 typ. .020 typ. .040 typ. .100 .090 .600 .300 max. .270 typ. .010 typ. .050 typ. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 commercial gull-wing (pdu13f-xxa2) .130 .030 .820 max. 1 2 3 4 5 6 7 8 14 13 12 11 10 9 .320 max. .018 typ. .410 typ. .300 typ. .020 typ. .600 typ. .020 typ. .100 typ. military dip (pdu13f-xxm) .880 .020 .882 .005 .020 typ. .040 typ. .100 .090 .700 .280 max. .590 max. .010 .002 .050 .010 .710 .005 .007 .005 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 military gull-wing (pdu13f-xxmc3)
pdu13f doc #97001 data delay devices, inc. 5 1/10/97 3 mt. prospect ave. clifton, nj 07013 delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c load: 1 fast-ttl gate supply voltage ( vcc): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 w max. rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 1.5 x total delay period: per in = 4.5 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. out out trig in ref trig test setup device under test (dut) time interval counter pulse generator computer system printer in timing diagram for testing td ar td af per in pw in t rise t fall 0.6v 0.6v 1.5v 1.5v 2.4v 2.4v 1.5v 1.5v v ih v il v oh v ol input signal output signal
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